Filter
Top Products
Section 19 Serial I/O with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 943 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
19.3.1 Mode Register (SIMDR)
SIMDR sets the operating mode for this module.
Bit:
Initial Value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R R R
TRMD1 TRMD0SYNCAT REDG FL3 FL2 FL1 FL0 TXDIZ -
SYNCAC
SYNCDL
----
Bit Bit Name
Initial
Value R/W Description
15
14
TRMD1
TRMD0
1
0
R/W
R/W
Transfer Mode 1, 0
Select transfer mode.
00: Slave mode
01: Setting prohibited
10: Master mode
11: Setting prohibited
13 SYNCAT 0 R/W SIOFSYNC Pin Valid Timing
Indicates the position where the SIOFSYNC signal is
output. This bit is valid in master mode.
0: At the start-bit data of frame
1: At the last-bit data of slot
Note: If this bit is set to 1, make sure that valid data is
transmitted/received or transmitted.
12 REDG 0 R/W Receive Data Sampling Edge
This bit is valid in master mode.
0: The SIOFRxD signal is sampled at the falling edge of
SIOFSCK (The SIOFTxD signal is transmitted at the
rising edge of SIOFSCK.)
1: The SIOFRxD signal is sampled at the rising edge of
SIOFSCK (The SIOFTxD signal is transmitted at the
falling edge of SIOFSCK.)