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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1595 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.17 Bus Control Registers (GRCBUSCNT1 and GRCBUSCNT2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
151413121110987654321
0
0000000000000000
RRRRRRRRRRRRRRRR
0000000000000000
RRRRRRRR/WRRRR/WRRRR/W
------
-
----------
----- -
BURST_
MODE
---
BUS_
FORMAT
---
ENDIAN
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 9 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
8 BURST_
MODE
0 R/W Selects the mode of transfer through the I bus
(GRCBUSCNT1: IV3-BUS; GRCBUSCNT2: IV4-
BUS). Reading out from the areas except the
large-capacity on-chip RAM requires this bit to be
set to 0.
0: 16-byte burst transfer
1: 128-byte burst transfer
7 to 5 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
4 BUS_
FORMAT
0 R/W Specifies the data format for the I bus
(GRCBUSCNT1: IV3-BUS; GRCBUSCNT2: IV4-
BUS).
0: RGB 565 format
1: RGB 4444 format
3 to 1 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 ENDIAN 0 R/W Specifies the endian for the I bus (GRCBUSCNT1:
IV3-BUS; GRCBUSCNT2: IV4-BUS).
0: Big endian
1: Little endian