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Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00 Page 897 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
18.3 Register Description
Table 18.2 lists the register configuration. Note that explanation in the text does not refer to the
channels.
Table 18.2 Register Configuration
Channel Register Name Abbreviation R/W Initial Value Address
Access
Size
0 Control register 0 SSICR_0 R/W H'00000000 H'FFFF0000 8, 16, 32
Status register 0 SSISR_0 R/W*
1
H'02000013 H'FFFF0004 8, 16, 32
FIFO control
register 0
SSIFCR_0 R/W H'00000000 H'FFFF0010 8, 16, 32
FIFO status register
0
SSIFSR_0 R/(W)*
2
H'00010000 H'FFFF0014 8, 16, 32
Transmit FIFO data
register 0
SSIFTDR_0 W Undefined H'FFFF0018 32
Receive FIFO data
register 0
SSIFRDR_0 R Undefined H'FFFF001C 32
1 Control register 1 SSICR_1 R/W H'00000000 H'FFFF0800 8, 16, 32
Status register 1 SSISR_1 R/W*
1
H'02000013 H'FFFF0804 8, 16, 32
FIFO control
register 1
SSIFCR_1 R/W H'00000000 H'FFFF0810 8, 16, 32
FIFO status register
1
SSIFSR_1 R/(W)*
2
H'00010000 H'FFFF0814 8, 16, 32
Transmit FIFO data
register 1
SSIFTDR_1 W Undefined H'FFFF0818 32
Receive FIFO data
register 1
SSIFRDR_1 R Undefined H'FFFF081C 32