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Section 16 Renesas Serial Peripheral Interface
Page 814 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(2) CPHA = 1
Figure 16.7 shows a sample transfer format for the serial transfer of 8-bit data when the CPHA bit
in the command register (SPCMD) is 1. In figure 16.7, RSPCK (CPOL = 0) indicates the RSPCK
signal waveform when the CPOL bit in SPCMD is 0; RSPCK (CPOL = 1) indicates the RSPCK
signal waveform when the CPOL bit is 1. The sampling timing represents the timing at which this
module fetches serial transfer data into the shift register. The input/output directions of the signals
depend on the modes (master or slave). For details, see section 16.4.2, Pin Control.
When the CPHA bit is 1, the driving of invalid data to the MOSI and MISO signals commences at
an SSL signal assertion timing. The driving of valid data to the MOSI and MISO signals
commences at the first RSPCK signal change timing that occurs after the SSL signal assertion.
After this timing, data is updated at every 1 RSPCK cycle. The transfer data fetch timing is always
1/2 RSPCK cycle after the data update timing. The settings in the CPOL bit do not affect the
RSPCK signal operation timing; they only affect the signal polarity.
t1, t2, and t3 are the same as those in the case of CPHA = 0. For a description of t1, t2, and t3
when this module is in master mode, see section 16.4.3 (1), Master/Slave (with This LSI Acting as
Master).
12345678
MOSI
MISO
SSL
t1 t2
t3
Start
Serial transfer period
End
RSPCK
cycle
Sampling
timing
RSPCK
(CPOL = 1)
RSPCK
(CPOL = 0)
Figure 16.7 Transfer Format (CPHA = 1)