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Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00 Page 793 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
16.3.8 Bit Rate Register (SPBR)
SPBR sets the bit rate in master mode. If the contents of SPBR are changed while the MSTR and
SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master
mode, the subsequent operation cannot be guaranteed.
76543210
Bit:
Initial value:
R/W:
11111111
R/W R/W R/W R/W R/W R/W R/W R/W
SPR7 SPR6 SPR5 SPR4 SPR3 SPR2 SPR1 SPR0
When this module is used in slave mode, the bit rate depends on the bit rate of the input clock
regardless of the settings of SPBR and BRDV.
The bit rate is determined by combinations of SPBR settings and the bit settings in the BRDV1
and BRDV0 bits in the command registers (SPCMD0 to SPCMD3). The equation for calculating
the bit rate is given below. In the equation, n denotes an SPBR setting (0, 1, 2, …, 255), and N
denotes bit settings in the bits BRDV1 and BRDV0 (0, 1, 2, 3).
Bit rate =
f (Bφ)
2 × (n + 1) × 2
N
Table 16.3 shows examples of the relationship between the SPBR register and BRDV1 and
BRDV0 bit settings.