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Section 9 Bus State Controller
Page 242 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
0 HIZCNT* 0 R/W High-Z Control
Specifies the state in software standby mode, deep
standby mode, or bus-released state for CKE, RAS,
and CAS.
0: High impedance in software standby mode, deep
standby mode, or bus-released state for CKE, RAS,
and CAS.
1: Driven in software standby mode, deep standby
mode, or bus-released state for CKE, RAS, and
CAS.
Note: * For High-Z control of CKIO, see section 5, Clock Pulse Generator.
9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 6)
CSnBCR is a 32-bit readable/writable register that specifies the memory connected to each space,
the number of idle cycles between bus cycles, and the bus width.
Do not access external memory for the corresponding area until CSnBCR initial setting and pin
setting are completed.
Idle cycles may be inserted even when they are not specified. For details, see section 9.5.11, Wait
between Access Cycles.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0011011011011011
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0000010000000000
R R/W R/W R/W R/W R/W R/W R R R R R R R R R
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
- IWW[2:0] IWRWD[2:0] IWRWS[2:0] IWRRD[2:0] IWRRS[2:0]
- TYPE[2:0] ENDIAN BSZ[1:0] - - - - - - - - -