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Section 17 I
2
C Bus Interface 3
Page 888 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
*
1
*
1
*
1
V
IH
*
2
*
2
SCL
V
IH
*
2
V
IH
*
2
V
IH
Time for
monitoring SCL
Time for
monitoring SCL
Time for
monitoring SCL
SCL pin
SCL pin
SCL pin
Time for
monitoring SCL
Synchronous clock
Synchronous clock
Synchronous clock
Internal
delay
Internal
delay
Internal
delay
Internal
delay
The frequency is not
the setting frequency.
(c) When the rising speed of SCL is lowered
(b) When SCL is driven to low by the slave device
(a) SCL is normally driven
SCL is not driven to low.
The monitor value
is high level.
The monitor value
is high level.
The monitor value
is low level.
The monitor value is
high level.
The monitor value is low level.
Notes: 1. The clock is set according to table 17.3 Transfer Rate.
2. When the NF2CYC bit in NF2CYC (NF2CYC) is set to 0, the internal delay time is 3 to 4 t
pcyc
.
When this bit is set to 1, the internal delay time is 4 to 5 t
pcyc
.
SCL is not driven to low.
SCL is driven to low by
the slave device.
Internal SCL monitor
Internal SCL monitor
Internal SCL monitor
Figure 17.22 Bit Synchronous Circuit Timing