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Section 21 IEBus
TM
Controller
R01UH0134EJ0400 Rev. 4.00 Page 1105 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
4 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
3 RE 0 R/W Receive Enable
Enables/disables reception. This bit must be set at the
initial setting before frame reception.
0: Reception is disabled.
1: Reception is enabled.
2 to 0 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
21.3.2 IEBus Command Register (IECMR)
IECMR issues commands to control communications. Since this register is a write-only register,
the read value is undefined.
76543210
00000000
-----
WWW
Bit:
Initial value:
R/W:
----- CMD
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 0 Reserved
These bits are always read as 0. The write value should
always be 0.