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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 261 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
1, 0 HW[1:0] 00 R/W Delay Cycles from RD,
W
En Negation to Address,
CS5 Negation
These bits specify the number of delay cycles from
RD and WEn negation to address and CS5 negation
when area 5 is specified as normal space or SRAM
with byte selection. They specify the number of delay
cycles from RD and WEn negation to CS5 negation
when area 5 is specified as MPX-I/O.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles