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Section 35 Motor Control PWM Timer
R01UH0134EJ0400 Rev. 4.00 Page 1829 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 35 Motor Control PWM Timer
This LSI has two channels of on-chip motor control PWM (pulse width modulator) timer with a
maximum capability of eight pulse outputs for each channel.
35.1 Features
Maximum of 16 pulse outputs
Two 10-bit PWM channels, each with eight outputs.
10-bit counter (PWCNT) and cycle register (PWCYR).
Duty and output polarity can be set for each output.
Automatic data transfer in every cycle
Each of four duty registers (PWDTR) is provided with buffer registers (PWBFR), with data
transferred automatically every cycle.
Duty settings selectable
A duty cycle of 0 to 100 can be selected by means of a duty register setting.
Counting clock selectable
There is a choice of five counting clocks (P, P/2, P/4, P/8, P/16).
High-speed access via internal 16-bit bus
Two interrupt sources
An interrupt can be requested independently for each channel by a cycle register compare
match.
Automatic transfer of register data
Block transfer and one-word data transfer are available by activating the direct memory
access controller.
Module stop mode can be set