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Section 11 Multi-Function Timer Pulse Unit 2
Page 576 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
TCNT_3
TCNT_4
TCNT_3
TCNT_4
2
201 10
2
2
01 10
TITCR[6:4]
TITCNT[6:4]
Buffer register
Temporary register
General register
TITCR[6:4]
TITCNT[6:4]
Data
Data
Data
Data1
Data1
Data1
Data
Data
Data
Data1
Data1
Data1
Data2
Data2
Data2
(1)When rewriting the buffer register within 1 carrier cycle from TGIA_3 interrupt
(2)When rewriting the buffer register after passing 1 carrier cycle from TGIA_3 interrupt
TGIA_3 interrupt generation
Buffer register rewrite timing
Buffer register rewrite timing
Buffer register rewrite timing
TGIA_3 interrupt generation
TGIA_3 interrupt generation TGIA_3 interrupt generation
Buffer transfer-
enabled period
Buffer register
Temporary register
General register
Buffer transfer-
enabled period
Note: * The MD bits 3 to 0 = 1101 in TMDR_3, buffer transfer at the crest is selected.
The skipping count is set to two.
T3AEN and T4VEN are set to 1 and 0.
Figure 11.71 Example of Operation when Buffer Transfer is Linked with Interrupt
Skipping (BTE1 = 1 and BTE0 = 0)