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Section 22 Renesas SPDIF Interface
R01UH0134EJ0400 Rev. 4.00 Page 1153 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
22.4 Input/Output Pins
Table 22.1 shows the pin configuration.
Table 22.1 Pin Configuration
Channel Pin Name I/O Description
0 SPDIF_OUT Output Transmitter biphase-mark encoded SPDIF bitstream
1 SPDIF_IN Input Receiver biphase-mark encoded SPDIF bitstream
0, 1
(Common)
AUDIO_CLK Input External clock for audio
AUDIO_X1 Input Crystal resonator/external clock for audio
AUDIO_X2 Output
22.5 Renesas SPDIF (IEC60958) Frame Format
The Renesas SPDIF frame consists of two subframes (for channels 1 and 2), each of which
contains a 4-bit preamble, audio data of up to 24 bits, a V flag, a user bit, a channel status bit, and
an even parity bit. Figure 22.3 shows the subframe format. According to this format, the Renesas
SPDIF performs biphase-mark modulation (channel coding) that will make the transmission line's
DC component a minimum value.
Synchronization
preamble
Aux Audio sample word V U C P
03478 272831
L
S
B
M
S
B
L
S
B
V = Validity flag
U = User data
C = Channel status
P = Parity bit
B/M/W
Figure 22.3 Subframe Format