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Section 26 USB 2.0 Host/Function Module
Page 1390 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
26.3.16 Interrupt Status Register 0 (INTSTS0)
INTSTS0 is a register that indicates the status of the various interrupts detected.
This register is initialized by a power-on reset. By a USB bus reset, the DVST and DVSQ[2:0] bits
are initialized.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000/1*
1
0000
0/1*
3
0*
2
0*
2
0/1*
2
0000
R/W*
7
R/W*
7
R/W*
7
R/W*
7
R/W*
7
RRRRRRRR/W*
7
RRR
VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ[2:0] VALID CTSQ[2:0]
Bit Bit Name
Initial
Value R/W Description
15 VBINT 0 R/W*
7
VBUS Interrupt Status*
4
*
5
0: VBUS interrupts not generated
1: VBUS interrupts generated
This module sets this bit to 1 on detecting a level
change (high to low or low to high) in the VBUS pin
input value. This module sets the VBSTS bit to
indicate the VBUS pin input value. When the VBUS
interrupt is generated, repeat reading the VBSTS bit
until the same value is read several times to
eliminate chattering.
14 RESM 0 R/W*
7
Resume Interrupt Status*
4
*
5
*
6
0: Resume interrupts not generated
1: Resume interrupts generated
When the function controller function is selected, this
module sets this bit to 1 on detecting the falling edge
of the signal on the DP pin in the suspended state
(DVSQ = 1XX).
When the host controller function is selected, the
read value is invalid.