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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1071 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
nTCMR0
(1) Clear TCNTR by TCMR0 in Event-Trigger mode
(2) Interrupt generation by TCMR0/1/2 in Event-Trigger mode
(3) Interrupt generation by TCMR0 in Time-Trigger mode
(4) Interrupt generation by TCMR1/2 in Time-Trigger mode
(5) Time-triggered transmission request in Time-Trigger mode, during bus idle
TCNTR
TCMR0/1/2
TCNTR
Flag/interrupt
Flag/interrupt
Flag/interrupt
TCMR0
TCNTR
TCMR0/1/2
CYCTR
Tx-Trigger Time I
CYCTR
TEW (register value)
TEW counter
Transmission request
for MBI
Transmitted message
Delay = (1 Bit Timing + 8 clocks)
to (2 Bit Timings + 11 clocks)
nn - 1n - 2 2 31
0
n
nn - 1n - 2 n + 3 n + 4n + 2
n + 1
n
nn - 1n - 2 n + 3 n + 4n + 2
n + 1
n
nn - 1n - 2 n + 3 n + 4n + 2
n + 1
n
n + 1nn - 1 n + 4 n + 5n + 3
n + 2
2
SOF
002
1
Figure 20.23 Timing Diagram of Timer