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Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00 Page 2009 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Tr Tc Tnop Trw1TapTapTdeTd1TcTr
t
AD3
t
AD3
CKIO
A25 to A0
CSn
RD/WR
A12/A11
*
1
D15 to D0
RAS
CAS
BS
CKE
DQMxx
DACKn
TENDn
t
AD3
t
AD3
t
AD3
t
AD3
*
2
Row
address
Column
address
Row
address
Column
address
t
AD3
t
AD3
t
AD3
t
AD3
t
AD3
t
AD3
t
AD3
t
CSD2
t
RWD2
t
RWD2
t
RWD2
t
CASD2
t
CASD2
t
CASD2
t
CASD2
t
CASD2
t
RASD2
t
RASD2
t
RASD2
t
RASD2
t
BSD
t
BSD
t
BSD
t
BSD
t
DQMD2
t
DQMD2
t
DQMD2
t
DQMD2
t
RDS4
t
RDH4
t
WDD3
t
WDH3
t
CSD2
t
CSD2
t
CSD2
t
DACD
t
DACD
t
DACD
t
DACD
WRITA
Command
READA
Command
(High) (High)
Figure 37.34 Synchronous DRAM Access Timing in Low-Frequency Mode
(Auto-Precharge, TRWL = 2 Cycles)