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Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00 Page 1299 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
17 DOCMD2 0 R/W Second Command Stage Execution Specification
Specifies whether or not the second command stage is
executed in command access mode.
0: Does not execute the second command stage
1: Executes the second command stage
16 DOCMD1 0 R/W First Command Stage Execution Specification
Specifies whether or not the first command stage is
executed in command access mode.
0: Does not execute the first command stage
1: Executes the first command stage
15 to 0 SCTCNT
[15:0]
H'0000 R/W Sector Transfer Count Specification [15:0]
Specify the number of sectors to be read continuously
in sector access mode. These bits are counted down for
each sector transfer end and stop when they reach 0.
These bits are used together with SCTCNT[19:16].
In command access mode, these bits are H'0 0001.