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Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00 Page 829 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(1) Overrun Error
If serial transfer ends when the receive buffer of the data register (SPDR) is full, this module
detects an overrun error, and sets the OVRF bit in SPSR to 1. When the OVRF bit is 1, this
module does not copy data from the shift register to the receive buffer so that the data prior to the
occurrence of the error is retained in the receive buffer. To reset the OVRF bit in SPSR to 0, either
perform a power-on reset, or write a 0 to the OVRF bit after SPSR has been read with the OVRF
bit set to 1.
Figure 16.14 shows an example of operation of the SPRF and OVRF bits in SPSR. The SPSR and
SPDR accesses shown in figure 16.14 indicates the condition of accesses to SPSR and SPDR,
respectively, where I denotes an idle cycle, W a write cycle, and R a read cycle. In the example of
figure 16.14, this module performs an 8-bit serial transfer in which the CPHA bit in the command
register (SPCMD) is 1, and CPOL is 0. The numbers given under the RSPCK waveform represent
the number of RSPCK cycles (i.e., the number of transferred bits).
SPDR access
SPRF
OVRF
RSPCK
(CPHA = 1, CPOL= 0)
8765432187654321
(4)(3)(2)(1)
I
I
I
R
SPSR access
IW
R
Figure 16.14 SPRF and OVRF Bit Operation Example