Filter
Top Products
Section 1 Overview
Page 2 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 1.1 SH7262/7264 Features
Items Specification
CPU
Renesas original SuperH architecture
Compatible with SH-1, SH-2, and SH-2E at object code level
32-bit internal data bus
Support of an abundant register-set
Sixteen 32-bit general registers
Four 32-bit control registers
Four 32-bit system registers
Register bank for high-speed response to interrupts
RISC-type instruction set (upward compatible with SH series)
Instruction length: 16-bit fixed-length basic instructions for improved
code efficiency and 32-bit instructions for high performance and
usability
Load/store architecture
Delayed branch instructions
Instruction set based on C language
Superscalar architecture to execute two instructions at one time
including a floating-point unit
Instruction execution time: Up to two instructions/cycle
Address space: 4 Gbytes
Internal multiplier
Five-stage pipeline
Harvard architecture