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Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00 Page 553 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(i) Initial Output in Complementary PWM Mode
In complementary PWM mode, the initial output is determined by the setting of bits OLSN and
OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P
in timer output control register 2 (TOCR2).
This initial output is the PWM pulse non-active level, and is output from when complementary
PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in
the dead time register (TDDR). Figure 11.44 shows an example of the initial output in
complementary PWM mode.
An example of the waveform when the initial PWM duty value is smaller than the TDDR value is
shown in figure 11.45.
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TGRA_4
TDDR
TCNT_3
TCNT_4
Initial output
Dead time
Time
Active level
Active level
TCNT_3, 4 count start
(TSTR setting)
Complementary
PWM mode
(TMDR setting)
Positive phase
output
Negative phase
output
Figure 11.44 Example of Initial Output in Complementary PWM Mode (1)