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Section 15 Serial Communication Interface with FIFO
Page 726 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
6 TEND 1 R/(W)* Transmit End
Indicates that when the last bit of a serial character
was transmitted, SCFTDR did not contain valid data,
so transmission has ended.
0: Transmission is in progress
[Clearing condition]
TEND is cleared to 0 when 0 is written after 1 is
read from TEND after transmit data is written in
SCFTDR*
1
1: End of transmission
[Setting conditions]
TEND is set to 1 when the chip is a power-on
reset
TEND is set to 1 when TE is cleared to 0 in the
serial control register (SCSCR)
TEND is set to 1 when SCFTDR does not contain
receive data when the last bit of a one-byte serial
character is transmitted
Note: 1. Do not use this bit as a transmit end flag
when the direct memory access controller
writes data to SCFTDR due to a TXI
interrupt request.