Filter
Top Products
Section 7 Interrupt Controller
Page 174 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
When canceling software standby mode by the NMI interrupt, set the NMIM bit to 0 to enable
the NMI interrupt request after confirming that the NMI interrupt request has been cleared in
the NMIF. If software standby mode is entered when the NMIM bit is 1 (NMI interrupt request
is masked), the NMI interrupt cannot cancel software standby mode. In this case, the NMI
edge cannot be detected in software standby mode and the NMI interrupt is not generated even
if software standby mode is canceled by cancel source other than NMI. When the NMI pin
keeps level (low level after the falling edge or high level after the rising edge) in software
standby mode until software standby mode is canceled by cancel source other than NMI (until
the clock is initiated after the oscillation settling), that edge of the NMI in software standby
mode can be detected.
When deep standby mode is entered, deep standby mode is canceled by the NMI interrupt
regardless of the NMI mask bit setting. NMIM bit is initialized by a power-on reset after
canceling deep standby mode.
When a sleep instruction is to be executed after 0 has been written to the NMIM bit (enabling
the NMI), read the value of the NMIM bit before executing the sleep instruction.
7.4.2 User Debugging Interface Interrupt
The user debugging interface interrupt has a priority level of 15, and occurs at serial input of a
user debugging interface interrupt instruction. User debugging interface interrupt requests are
edge-detected and retained until they are accepted. The user debugging interface interrupt
exception handling sets the I3 to I0 bits in SR to level 15. For user debugging interface interrupts,
see section 34, User Debugging Interface.
7.4.3 IRQ Interrupts
IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge,
rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense
select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The
priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority
registers 01 and 02 (IPR01 and IPR02).
When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the interrupt
controller while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent
to the interrupt controller when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt
requests can be checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ
interrupt request register (IRQRR).
When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the
IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the interrupt controller. The
result of IRQ interrupt request detection is retained until that interrupt request is accepted.