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Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00 Page 933 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
18.4.5 Receive Operation
Like transmission, reception can be controlled either by DMA transfer or interrupt.
Figures 18.22 and 18.23 show the flow of operation.
When disabling this module, the clock* must be kept supplied to this module until the IIRQ bit
indicates that the module is in the idle state.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Oversampling clock when SCKD = 1.