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Section 21 IEBus
TM
Controller
R01UH0134EJ0400 Rev. 4.00 Page 1113 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
21.3.9 IEBus Reception Master Address Register 1 (IEMA1)
IEMA1 indicates the lower four bits of the communication destination master unit address in
slave/broadcast reception.
76543210
00000000
RRRRRRRR
Bit:
Initial value:
R/W:
IMAL4 - - - -
Bit Bit Name
Initial
Value R/W Description
7 to 4 IMAL4 0000 R Lower Four Bits of IEBus Reception Master Address
Indicates the lower four bits of the communication
destination master unit address in slave/broadcast
reception. This register is enabled when
slave/broadcast reception starts, and the contents are
changed at the time of setting the RXS flag. If a
broadcast receive error interrupt is selected by the DEE
bit in IECTR and the receive buffer is not in the receive
enabled state at control field reception, a receive error
interrupt is generated and the lower four bits of the
master address are stored in IEMA1.
3 to 0 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.