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Section 19 Serial I/O with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 971 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(2) Reception in Master Mode
Figure 19.7 shows an example of reception settings and operation when this module is used as a
master.
Start
No
Ye s
No
Ye s
End
No.
1
2
3
4
5
6
7
8
Set SIMDR, SISCR, SIRDAR,
and SIFCTR
Set the SCKE bit in SICTR to 1
Start SIOFSCK output
Set the FSE and RXE bits
in SICTR to 1
RDREQ = 1?
Reception
ended?
Clear the RXE bit in SICTR to 0
Set operating mode, serial clock,
slot position for receive data,
and FIFO request threshold
value
Set operation start for baud rate
generator
Output serial clock
Flow Chart Settings of This Module
Operation of This Module
Set the start for frame synchronous
signal output and enable
reception
Issue receive transfer
request according to the
receive FIFO threshold
value
Reception
End reception
Output frame synchronous
signal
Read receive data
Set to disable reception
Read SIRDR
Store SIOFRXD receive data in SIRDR
synchronously with SIOFSYNC
Figure 19.7 Example of Receive Operation in Master Mode