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Section 9 Bus State Controller
Page 334 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Tc1Tr Td1 Tde Tap Tr Tc1 Tnop
Trwl
Tap
(High)
CKIO
CKE
A25 to A0
CSn
RD/WR
RAS
DQMx
D15 to D0
BS
DACKn*
2
A12/A11*
1
CAS
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.28 Low-Frequency Mode Access Timing