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Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00 Page 899 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
18.3.1 Control Register (SSICR)
SSICR is a readable/writable 32-bit register that controls the IRQ, selects the polarity status, and
sets operating mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
Initial value:
R/W:
1514131211109876543210
Bit:
Initial value:
R/W:
0000000000000000
R R/W R/W R/W RR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W
TUIEN TOIEN -RUIEN ROIEN IIEN CHNL[1:0] DWL[2:0] SWL[2:0]
SCKD SWSD
- CKS
SCKP SWSP SPDP SDTA PDTA DEL CKDV[3:0] MUEN -TEN REN
Bit Bit Name
Initial
Value R/W Description
31 0 R Reserved
The read value is undefined. The write value should
always be 0.
30 CKS 0 R/W Oversampling Clock Select
Selects the clock source for oversampling.
0: AUDIO_X1 input
1: AUDIO_CLK input
29 TUIEN 0 R/W Transmit Underflow Interrupt Enable
0: Disables an underflow interrupt.
1: Enables an underflow interrupt.
28 TOIEN 0 R/W Transmit Overflow Interrupt Enable
0: Disables an overflow interrupt.
1: Enables an overflow interrupt.
27 RUIEN 0 R/W Receive Underflow Interrupt Enable
0: Disables an underflow interrupt.
1: Enables an underflow interrupt.
26 ROIEN 0 R/W Receive Overflow Interrupt Enable
0: Disables an overflow interrupt.
1: Enables an overflow interrupt.