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Section 1 Overview
R01UH0134EJ0400 Rev. 4.00 Page 25 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Classification Symbol I/O Name Function
NAND flash
memory
controller
FALE O Flash memory
address latch
enable
Asserted for address output and
negated for data I/O.
Negated at data input/output.
FRE O Flash memory
read enable
Reads data at falling edge.
FCE O Flash memory
chip enable
Enables the flash memory connected
to this LSI.
FCLE O Flash memory
command latch
enable
Asserted at command output.
FRB I Flash memory
ready/busy
High level indicates ready state and
low level indicates busy state.
FWE O Flash memory
write enable
Flash memory latches commands,
addresses, and data at rising edge.
NAF7 to NAF0 I/O Flash memory
data
Data I/O pins.
USB 2.0
host/function
module
DP I/O USB 2.0
host/function
module D+ data
D+ data pin for USB 2.0 host/function
module bus.
DM I/O USB 2.0
host/function
module D– data
D– data pin for USB 2.0 host/function
module bus.
VBUS I VBUS input Connected to Vbus on USB 2.0
host/function module bus.
REFRIN I Reference input Connected to USBAPVss via
5.6-k 1% resistance.
USB_X1 I Crystal
resonator/
external clock for
USB 2.0
host/function
module
Connected to a crystal resonator for
USB 2.0 host/function module. An
external clock signal may also be
input to the USB_X1 pin.
USB_X2 O
USBAPVcc I Power supply for
transceiver
analog pins
Power supply for pins.