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Section 5 Clock Pulse Generator
Page 122 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
5.4 Register Descriptions
Table 5.4 shows the register configuration of the clock pulse generator.
Table 5.4 Register Configuration
Register Name Abbreviation R/W Initial Value Address Access Size
Frequency
control register
FRQCR R/W Modes 0 and 1: H'0124
Modes 2 and 3: H'0013
H'FFFE0010 16
5.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the
CKIO pin during normal operation mode, release of bus mastership, change of gain of crystal
oscillator for the XTAL pin, software standby mode, and standby mode cancellation. The register
specifies the frequency division ratio for the CPU clock and peripheral clock (P). FRQCR is
accessed by word.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000000/1* 0 0 0/1* 1/0* 0 1/0* 0/1* 0/1*
R R/W R/W R/W R R R R R R R/W R/W R R/W R/W R/W
Bit:
Initial value:
R/W:
-
CKO
EN2
CKOEN[1:0] - - IFC[1:0] - PFC[2:0]
- - STC -
Note: * The initial value changes depending on the clock mode.
Bit Bit Name
Initial
Value R/W Description
15 0 R Reserved
This bit is always read as 0. The write value should
always be 0.