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Section 27 Video Display Controller 3
Page 1574 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.2 Video Interrupt Control Register (VIDEO_INT_CNT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
151413121110987654321
0
0000000000000000
R R R R/W R R R R/W R R R R/W R R R R/W
0000000000000000
RRRR/W*
3
R R R R/W*
3
R R R R/W*
3
R R R R/W*
3
---
INT_
V_EN
--
-
-
INT_
F_EN
---
INT_
UF_EN
---
INT_
OF_EN
---
V_
PERIOD
--
F_
END
---
UNDER_
FLOW
---
OVER_
FLOW
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value
R/W Description
31 to 29 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
28 INT_V_EN 0 R/W Enables output of interrupts for indicating VSYNC
cycle fluctuation detected in the input video.
0: Disabled
1: Enabled
27 to 25 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
24 INT_F_EN 0 R/W Enables output of write completion interrupts. Set
to 0 in video display mode.
0: Disabled
1: Enabled
23 to 21 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 INT_UF_EN 0 R/W Enables output of underflow interrupts
0: Disabled
1: Enabled
19 to 17 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.