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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 343 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count
16 bits 8 bits Not affected 1 1
16 bits Not affected 1 1
32 bits Not affected 2 1
16 bytes 00 8 1
01 2 4
10* 4 2
2, 4, 2 3
Note: * When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in
CSnWCR are 10, the number of bursts and access count depend on the access start
address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4
or H'xxxC, 2-4-2 burst access is performed.
CKIO
A25 to A0
RD
D15 to D0
DACKn*
Note: * The waveform for DACKn is when active low is specified.
WAIT
CSn
T1 Tw Tw T2B Twb T2B Twb T2B Twb T2
RD/WR
BS
Figure 9.33 Burst ROM Access Timing (Clocked Asynchronous)
(Bus Width = 16Bits, 16-Byte Transfer (Number of Burst 4-4), Wait Cycles Inserted in First
Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)