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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 369 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
When a memory access request by the NAND flash memory controller and an external bus release
request conflict with each other, the request accepted first has higher priority. When the two
requests occur at the same time, the access by the NAND flash memory controller has higher
priority.
Auto-refresh operation and self-refresh operation are executed even during a memory access by
the NAND flash memory controller.