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Section 16 Renesas Serial Peripheral Interface
Page 842 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(b) Terminating Serial Transfer
Irrespective of the CPHA bit in the command register 0 (SPCMD0), this module terminates the
serial transfer after detecting an RSPCK edge corresponding to the final sampling timing. When
the receive buffer has an enough space for receive data, this module copies received data from the
shift register to the receive buffer of the data register (SPDR) upon termination of the serial
transfer. Irrespective of the value of the SPRF bit, this module changes the status of the shift
register to "empty" upon termination of the serial transfer. If this module detects an SSL input
signal negation from the beginning of serial transfer to the end of serial transfer, a mode fault error
occurs (see section 16.4.6, Error Detection).
The final sampling timing changes depending on the bit length of the transfer data. In slave mode,
the data length depends on the settings in bits SPB3 to SPB0 bits in SPCMD0. The polarity of the
SSL input signal depends on the setting in the SSL0P bit in the slave select polarity register
(SSLP). For details on the transfer format, see section 16.4.4, Transfer Format.
(c) Notes on Slave Operations
If the CPHA bit in the command register 0(SPCMD0) is 0, this module starts serial transfers when
it detects the assertion edge for an SSL input signal. In the type of configuration shown in figure
16.4 as an example, if this module is used in single-slave mode, the SSL signal is always fixed at
active state. Therefore, when the CPHA bit is set to 0, this module cannot correctly start a serial
transfer. To correctly execute send/receive operation in a configuration in which the SSL input
signal is fixed at active state, the CPHA bit should be set to 1. When it is necessary to set the
CPHA bit to 0, the SSL input signal should not be fixed.
(d) Burst Transfer
If the CPHA bit in the command register 0 (SPCMD0) is 1, continuous serial transfer (burst
transfer) can be executed while retaining the assertion state for the SSL input signal. If the CPHA
bit is 1, the period from the first RSPCK edge to the sampling timing for the reception of the final
bit in an SSL signal active state corresponds to a serial transfer period. Even when the SSL input
signal remains at the active level, this module can accommodate burst transfers because it can
detect the start of access.
If the CPHA bit is 0, for the reason given in section 16.4.8 (2) (c), Notes on Slave Operations,
second and subsequent serial transfers during the burst transfer cannot be executed correctly.