Filter
Top Products
Section 22 Renesas SPDIF Interface
Page 1182 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
22.8.2 Transmitter Module Initialization
The device defaults to an idle state when it comes out of reset, or can be put into an idle state
when 0 is written to the TME bit in the CTRL register. When the transmitter module is idle, it has
the following settings:
The transmitter idle status bit (TIS) is set to 1, all other status bits are cleared to 0.
Preamble generation is invalid.
Synchronization between channels 1 and 2 is set to 0 (0 for channel 1, 1 for channel 2).
Both word_count and frame_count are set to 0.
The output from the biphase-mark encoder is set to 0.
Channel status, user and audio data registers will retain its value prior to putting the module into
idle. To exit the idle state the user must write 1 to the TME bit in the CTRL register.
22.8.3 Initial Settings for Transmitter Module
When the TME bit is set to 1, the TUIR and CSTX bits are set to 1. After that, if data is written in
the order of 1) TUI and 2) TLCS and TRCS, a channel status error will occur. To avoid this, be
sure to write data in the order of 1) TLCS and TRCS and 2) TUI.
Before writing the first audio data (write access to TLCA or TRCA by the CPU or write access to
TDAD by the DMA transfer) after setting the TME bit to 1, be sure to check that the CSTX and
TUIR bits are cleared by writing to TLCS, TRCS, and TUI.