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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1631 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 27.21 Calculations of Register Settings (registers are shaded in grey)
Register Name or Value Unit
(9) VIDEO_VSYNC_TIM2[9:0] (8) – 1 Line
(10) Difference in time between video input and
output to panel
(1) (2) – (3) (4) Line
(11) Conversion of number of buffers When (8) is negative: (10) / 3
When (8) is positive: (10) / 1
Line
(12) VIDEO_LINEBUFF_NUM[9:0] (11) + (5) Line
(13) VIDEO_VSYNC_TIM1[25:16]* When (8) is negative: (6) – (8) + (5) / 2
When (8) is positive:
(6) + (11) – (8) + (5) / 2
Line
(14) VIDEO_VSYNC_TIM1[9:0]* When (8) is negative: (7) – (8) + (5) / 2
When (8) is positive:
(7) + (11) – (8) + (5) / 5
Line
Note: * When (8) is negative, the data rate of the input video is larger than that of the video
output to the panel. In this case, after video data begins to be stored in the line buffer,
start reading from the buffer while only one to several lines of data are stored, so that
the buffer does not overflow.
When (8) is positive, the data rate of the input video is smaller than that of the video
output to the panel. In this case, start reading from the line buffer after the buffer has
stored enough input data, so that the buffer does not underflow (the line buffer does not
become empty).
Note that when the line buffer is large enough (for example, when the buffer can store
one field of data), the above restrictions are loosened.
Step 2: To place the video at the center or along the bottom end, calculate the new settings from
the values obtained in step 1.
Note: Video cannot be displayed in the last line of the panel.
Table 27.22 Calculation of Register Settings (registers are shaded in grey)
Calculation Expression Unit
(15)
VIDEO_VSYNC_TIM2[9:0] (9) + start line to display Line
(16) Conversion to the number of input video lines (3) start line to display / (1) Line
(17) VIDEO_VSYNC_TIM1[25:16] (13) – (16) Line
(18) VIDEO_VSYNC_TIM1[9:0] (14) – (16) Line