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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 303 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
T1
CKIO
A25 to A0
CS5
RD/WR
RD
WEn
BS
Read
Write
T2
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Ta1 Ta3 Th
AH
Address
Address
Data
Data
TfTa2
D15/D7 to D0
D15/D7 to D0
Figure 9.11 (2) Access Timing for MPX Space (Address Cycle No Wait, Assert Extension
Cycle 1.5, Data Cycle No Wait, Negate Extension Cycle 1.5)