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Section 37 Electrical Characteristics
Page 2006 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Tr c Tr cTrrTpwTp Trc
t
CSD1
t
AD1
t
AD1
t
RWD1
t
RWD1
t
RWD1
t
CSD1
t
CSD1
t
CSD1
t
RASD1
t
RASD1
t
RASD1
t
RASD1
t
AD1
t
AD1
CKIO
A25 to A0
CSn
RD/WR
A12/A11
*
1
D15 to D0
RAS
t
CASD1
t
CASD1
CAS
(High)
(Hi-Z)
BS
CKE
DQMxx
DACKn
TENDn
*
2
Figure 37.31 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles)