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Section 37 Electrical Characteristics
Page 2002 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Tc3 Tc4 TdeTc2
Td1 Td2 Td3 Td4
Tc1TrTrwTp
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
t
AD1
t
AD1
t
RWD1
t
RWD1
t
RWD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
CKIO
A25 to A0
CSn
RD/WR
A12/A11
*
1
D15 to D0
t
RASD1
t
RASD1
t
RASD1
t
RASD1
RAS
READ command
Column
address
Row
address
t
CASD1
t
CASD1
CAS
t
BSD
t
BSD
(High)
BS
CKE
t
DQMD1
t
DQMD1
DQMxx
t
DACD
t
DACD
DACKn
TENDn
*
2
t
RDH2
t
RDS2
t
RDH2
t
RDS2
Figure 37.27 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses,
CAS Latency 2, WTRCD = 0 Cycle)