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Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00 Page 1337 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
25.4.7 Status Read
This module can read the status register of an AND/NAND-type flash memory. The data in the
status register is input through the I/O7 to I/O0 pins and stored in the bits STAT[7:0] in
FLBSYCNT, which can be read by the CPU. If a program error or erase error is detected when the
status register value is stored in the bits STAT[7:0] in FLBSYCNT, the STERB bit in
FLINTDMACR is set to 1 and generates an interrupt to the CPU if the STERINTE bit in
FLINTDMACR is enabled. If a status error occurs during continuous sector access, the TREND
bit in FLTRCR is set to 1 and the procedure stops.
(1) Status Read of NAND-Type Flash Memory
The status register of NAND-type flash memory can be read by inputting command H'70 to
NAND-type flash memory. If programming is executed in command access mode or sector access
mode while the DOSR bit in FLCMDCR is set to 1, this module automatically inputs command
H'70 to NAND-type flash memory and reads the status register of NAND-type flash memory.
When the status register of NAND-type flash memory is read, the I/O7 to I/O0 pins indicate the
following information as described in table 25.3.
Table 25.3 Status Read of NAND-Type Flash Memory
I/O Status (definition) Description
I/O7 Program protection 0: Cannot be programmed
1: Can be programmed
I/O6 Ready/busy 0: Busy state
1: Ready state
I/O5 to I/O1 Reserved
I/O0 Program/erase 0: Pass
1: Fail