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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 361 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 9.17 Minimum Number of Idle Cycles on Internal Bus (CPU Operation)
CPU Operation
Clock Ratio (I:B)
8:1 6:1 4:1 3:1 2:1 1:1
Write write 1 1 2 2 2 3
Write read 0 0 0 0 0 1
Read write 1 1 2 2 2 3
Read read 0 0 0 0 0 1
Table 9.18 Minimum Number of Idle Cycles on Internal Bus (Direct Memory Access
Controller Operation)
Direct Memory Access
Controller Operation
Transfer Mode
Dual Address Single Address
Write write 0 2
Write read 0 or 2 0
Read write 0 0
Read read 0 2
Notes: 1. The write write and read read columns in dual address transfer indicate the cycles
in the divided access cycles.
2. For the write read cycles in dual address transfer, 0 means different channels are
activated successively and 2 means when the same channel is activated successively.
3. The write read and read write columns in single address transfer indicate the case
when different channels are activated successively. The "write" means transfer from a
device with DACK to external memory and the "read" means transfer from external
memory to a device with DACK.