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Section 26 USB 2.0 Host/Function Module
Page 1464 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 26.14 (1) Information Cleared by this Module by Setting ACLRM = 1
No. Information Cleared by ACLRM Bit Manipulation
1 All the information in the FIFO buffer assigned to the pertinent pipe
2 When the host controller function is selected, the interval count value when the pertinent
pipe is for isochronous transfer
Table 26.14 (2) Cases That Require Setting ACLRM to 1
No. Cases in which Clearing the Information is Necessary
1 When it is necessary to clear all the information assigned to the pertinent pipe from the
FIFO buffer
2 When the interval count value is to be reset
3 When the BFRE setting is modified
4 When the transaction count function is forcibly terminated
26.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)
PIPEnTRE is a register that enables or disables the transaction counter corresponding to PIPE1 to
PIPE5, and clears the transaction counter.
This register is initialized by a power-on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000000000000000
R R R R R R/W R/W*
1
R RRRRRRRR
——————TRENBTRCLR—————— —
—
Bit Bit Name
Initial
Value R/W Description
15 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.