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Section 10 Direct Memory Access Controller
Page 390 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
17 AM 0 R/W Acknowledge Mode
Specifies whether DACK and TEND are output in data
read cycle or in data write cycle in dual address mode.
In single address mode, DACK and TEND are always
output regardless of the specification by this bit.
This bit is valid only in CHCR_0 and CHCR_1*
1
. This
bit is reserved in CHCR_2 to CHCR_15*
2
; it is always
read as 0 and the write value should always be 0.
0: DACK and TEND output in read cycle (dual address
mode)
1: DACK and TEND output in write cycle (dual address
mode)
16 AL 0 R/W Acknowledge Level
Specifies the DACK (acknowledge) signal output is
high active or low active.
This bit is valid only in CHCR_0 and CHCR_1*
1
. This
bit is reserved in CHCR_2 to CHCR_15*
2
; it is always
read as 0 and the write value should always be 0.
0: Low-active output from DACK
1: High-active output from DACK