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Section 18 Serial Sound Interface
Page 906 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
0 REN 0 R/W Receive Enable
0: Disables the receive operation.
1: Enables the receive operation.
18.3.2 Status Register (SSISR)
SSISR consists of status flags indicating the operational status of this module and bits indicating
the current channel numbers and word numbers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
Initial value:
R/W:
1514131211109876543210
Bit:
Initial value:
R/W:
001
UndefinedUndefined UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
R R R/(W)*R/(W)*R/(W)*R/(W)* RRRRRRRRRR
UndefinedUndefinedUndefinedUndefined
UndefinedUndefined
00
UndefinedUndefinedUndefinedUndefinedUndefined
0010011
RRRRRRRRRRRRRRRR
- - TUIRQ TOIRQ RUIRQ ROIRQ IIRQ -- -------
---------TCHNO[1:0] TSWNORCHNO[1:0] RSWNO IDST
Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.
Bit Bit Name
Initial
Value
R/W Description
31, 30
Undefined R Reserved
The read value is undefined. The write value should
always be 0.
29 TUIRQ 0 R/(W)* Transmit Underflow Error Interrupt Status Flag
This status flag indicates that transmit data was
supplied at a lower rate than was required.
This bit is set to 1 regardless of the value of the TUIEN
bit and can be cleared by writing 0 to this bit.
If TUIRQ = 1 and TUIEN = 1, an interrupt occurs.
If TUIRQ = 1, SSITDR did not have data written to it
before it was required for transmission. This will lead to
the same data being transmitted once more and a
potential corruption of multi-channel data. As a result,
this module will output erroneous data.
Note: When an underflow error occurs, the current data
in the data buffer of this module is transmitted
until the next data is written.