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Section 10 Direct Memory Access Controller
Page 420 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(b) Single Address Mode
In single address mode, both the transfer source and destination are external devices, either of
them is accessed (selected) by the DACK signal, and the other device is accessed by an address. In
this mode, this module performs one DMA transfer in one bus cycle, accessing one of the external
devices by outputting the DACK transfer request acknowledge signal to it, and at the same time
outputting an address to the other device involved in the transfer. For example, in the case of
transfer between external memory and an external device with DACK shown in figure 10.5, when
the external device outputs data to the data bus, that data is written to the external memory in the
same bus cycle.
External address bus External data bus
Direct memory
access controller
External
memory
DACK
DREQ
Data flow (from memory to device)
Data flow (from device to memory)
External device
with DACK
This LSI
Figure 10.5 Data Flow in Single Address Mode
Two kinds of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and external memory. In both cases, only the external request signal (DREQ) is used
for transfer requests.