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Section 18 Serial Sound Interface
Page 902 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
13 SCKP 0 R/W Serial Bit Clock Polarity
0: SSIWS and SSIDATA change at the SSISCK falling
edge (sampled at the SCK rising edge).
1: SSIWS and SSIDATA change at the SSISCK rising
edge (sampled at the SCK falling edge).
SCKP =0 SCKP = 1
SSIDATA input sampling timing at the time
of reception
SSISCK rising
edge
SSISCK falling
edge
SSIDATA output change timing at the time
of transmission
SSISCK falling
edge
SSISCK rising
edge
SSIWS input sampling timing at the time of
slave mode (SWSD = 0)
SSISCK rising
edge
SSISCK falling
edge
SSIWS output change timing at the time of
master mode (SWSD = 1)
SSISCK falling
edge
SSISCK rising
edge
12 SWSP 0 R/W Serial WS Polarity
0: SSIWS is low for 1st channel, high for 2nd channel.
1: SSIWS is high for 1st channel, low for 2nd channel.
11 SPDP 0 R/W Serial Padding Polarity
0: Padding bits are low.
1: Padding bits are high.
10 SDTA 0 R/W Serial Data Alignment
0: Transmitting and receiving in the order of serial data
and padding bits
1: Transmitting and receiving in the order of padding
bits and serial data