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Section 35 Motor Control PWM Timer
R01UH0134EJ0400 Rev. 4.00 Page 1835 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
7 OPSnH 0 R/W Output Polarity Select
Each of these bits selects the PWM output polarity.
0: PWM direct output
1: PWM inverse output
6 OPSnG 0 R/W
5 OPSnF 0 R/W
4 OPSnE 0 R/W
3 OPSnD 0 R/W
2 OPSnC 0 R/W
1 OPSnB 0 R/W
0 OPSnA 0 R/W
(n = 1, 2)
35.3.3 PWM Counter_n (PWCNT_n) (n = 1, 2)
PWCNT_n is a 10-bit up-counter incremented by the input clock. The input clock is selected by
clock select bits CKS2 to CKS0 in PWCR_n.
PWCNT_n can not be directly accessed by the CPU. PWCNT_n is initialized to H'FC00, when the
CST bit in PWCRn is cleared to 0.
35.3.4 PWM Cycle Register_n (PWCYR_n) (n = 1, 2)
PWCYR_n is a 16-bit readable/writable register that sets the PWM conversion cycle.
15 14 13 12 11 10 9 8
Bit:
Initial value:
R/W:
11111111
R/W R/W R/W R/W R/W R/W R/W R/W
PWC
Y15
PWC
Y14
PWC
Y13
PWC
Y12
PWC
Y11
PWC
Y10
PWC
Y9
PWC
Y8
76543210
Bit:
Initial value:
R/W:
11111111
R/W R/W R/W R/W R/W R/W R/W R/W
PWC
Y7
PWC
Y6
PWC
Y5
PWC
Y4
PWC
Y3
PWC
Y2
PWC
Y1
PWC
Y0
When a PWCYR_n compare match occurs, PWCNT_n is cleared and data is transferred from the
buffer register (PWBFR_n) to the duty register (PWDTR_n).
PWCYR_n should be written to only while PWCNT_n is stopped. A value of H'FC00 must not be
set to PWCYR_n.