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Section 27 Video Display Controller 3
Page 1562 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
@0000
02 03 04 05 06 07 08 09 0A 0B 0C 0E0D 0F00
RGB00
RGB08
RGB10
RGB20
RGB40
RGB01
RGB09
RGB11
RGB21
RGB41
01
@0010
@0100
@0200
@8000
:
:
:
:
:
:
Address
Base address (Example: 0000)
Field offset
(Example: 8000)
Line offset
(Example: 0100)
. . .
. . .
. . .
. . .
. . .
Figure 27.10 Schematic Diagram of Video Data Allocation on On-Chip Large-Capacity
RAM or SDRAM