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Section 25 NAND Flash Memory Controller
Page 1316 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
25.3.14 Bus Hold Time Setting Register (FLHOLDCR)
FLHOLDCR specifies the external bus release frequency if any other module (including the CPU)
accesses a memory under the control of the bus state controller while this module is writing to or
reading from the flash memory in sector access mode. With the HOLDEN bit = 0 in this register,
this module holds the external bus during transfers between the flash memory and this LSI. Note
that this may cause a deadlock depending on the program code and transfer data location and
usage.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
Initial value:
R/W:
1514131211109876543210
Bit:
Initial value:
R/W:
0000000000000000
RRRRRRRRRRRRRRRR
0000000000000000
RRRRRRRRRRRRRRRR/W
------
--
--
----
-----------
-
-
-
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HOLDEN
Bit Bit Name
Initial
Value
R/W Description
31 to 1 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0 HOLDEN 0 R/W Bus Hold Enable
Specifies whether to release the external bus
mastership during write to or read from the flash
memory in sector access mode.
0: Holds the bus mastership during transfers.
1: Releases the bus mastership during transfers if the
FIFO empty or full state is entered in sector access
mode.
Note: When using the FIFO in command access
mode, store the control program for this module
and transfer data in the on-chip RAM.