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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1599 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.19 Graphics Image Base Address Registers (GROPSADR1 and GROPSADR2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
151413121110987654321
0
0000000000000000
R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
- - - GROPSADR[28:16]
GROPSADR[15:0]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name Initial Value R/W Description
31 to 29 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
28 to 0 GROPSADR
[28:0]
H'00000000 R/W These bits specify the base address from which a
graphics image is to be read. The lowest bit should
always be 0.
Note: This module processes 16-bit RGB data; it cannot handle data located beyond a 2-byte
alignment boundary.
27.7.20 Graphics Image Size Registers (GROPSWH1 and GROPSWH2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
RRRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
0000000000000000
RRRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
------
-
GROPSH[9:0]
- - - - - GROPSW[9:0]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 26 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 16 GROPSH
[9:0]
H'000 R/W These bits specify the height of the graphics image
area in number of lines.