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Section 28 Sampling Rate Converter
Page 1656 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
1 IINT 1 R/(W)*
1
Input Data FIFO Empty Interrupt Request Flag
Indicates that the number of data units in the input
FIFO has become equal to or smaller than the
triggering number specified by the IFTRG1 and
IFTRG0 bits in the input data control register
(SRCIDCTRL).
[Clearing conditions]
When 0 has been written to the IINT bit after
reading IINT = 1.
When the number of data units in the input FIFO
has exceeded the specified triggering number due
to DMA transfer to the input FIFO.
[Setting conditions]
When the number of data units in the input FIFO
has become equal to or smaller than the specified
triggering number.
When 1 has been written to the CL bit in
SRCCTRL.
When 1 has been written to the SRCEN bit in
SRCCTRL while SRCEN is 0.