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Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00 Page 1339 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
25.7 Usage Notes
25.7.1 External Bus Mastership Release Timing
This module negates FCE regardless of the busy/ready state when having completed a necessary
process. With bit 21 (BUSYON) set to 0 in the common control register (FLCMNCR), this
module negates FCE and releases the bus mastership even during the busy state upon completion
of the process. With BUSYON = 0, setting bit 24 (DOSR) in the command control register
(FLCMDCR) to 1 to read the status enables acquiring the bus mastership even during the busy
state.
CLE
ALE
WE
CE
RE
I/O
R/B
H'80
H'10
Figure 25.17 BUSYON = 0, DOSR = 0 (Writing to Flash Memory)